Computer Architecture Memory and Bus

Understanding Memory Types: DRAM vs. SRAM

Dynamic Random‑Access Memory (DRAM) and Static Random‑Access Memory (SRAM) are the two most common volatile memory technologies used in modern computers. Although both store binary data, they differ fundamentally in how they retain that data.

• DRAM cells consist of a tiny capacitor paired with a transistor. The capacitor holds an electric charge that represents a bit ("1" or "0"). Over time this charge leaks, so the cell must be refreshed periodically—typically every few milliseconds—to restore the original value.
• SRAM cells are built from a small group of transistors that form a bistable latch. Because the latch continuously reinforces its state, no charge decay occurs, and therefore no refresh operation is required.

Understanding why DRAM needs refresh while SRAM does not is crucial for grasping trade‑offs such as density, speed, and power consumption. DRAM’s high density makes it ideal for main memory, whereas SRAM’s speed and simplicity make it perfect for caches and registers.

Address Bus Width and Addressable Memory Space

The address bus determines how many unique memory locations a processor can address. Each line (or wire) on the bus can be either low (0) or high (1), creating a binary combination.

With 24 address lines, the total number of distinct addresses is:

2²⁴ = 16,777,216 addresses.

Because most systems address memory at the byte level, each address corresponds to one byte. Therefore the maximum addressable memory size is:

16,777,216 bytes = 16 MiB × 256 = 4 GiB.

Visualize the 24‑line bus as 24 switches. Every possible on/off combination yields a unique address, just as a 24‑digit binary number can represent any value from 0 to 4,194,303 (in decimal), which translates to 4 GiB of addressable space.

The Role of the NorthBridge in Modern Chipsets

Historically, the NorthBridge (also called the Memory Controller Hub) was the central hub that linked the CPU to high‑speed components:

• It managed communication between the processor and main memory (RAM).
• It handled the connection to the graphics subsystem (PCI‑Express or AGP).
• It coordinated high‑performance I/O such as the PCI‑Express lanes.

In contemporary designs, many NorthBridge functions have been integrated directly into the CPU die, but the conceptual role—facilitating fast data exchange between the CPU and memory—remains a cornerstone of computer architecture.

Address Bus (ABus) vs. Data Bus (DBus) vs. Control Bus (CBus)

When a processor fetches an instruction from a specific memory location, it must convey that location to the memory subsystem. This is done via the address bus (ABus). The ABus carries the binary address (e.g., 0x00400000) while the data bus (DBus) transports the actual instruction or data bytes, and the control bus (CBus) carries timing and command signals that orchestrate the transaction.

Understanding the separation of these three buses helps explain why a single instruction fetch involves multiple coordinated signals across the system.

Cache Replacement Policies: Choosing Which Line to Evict

When a cache becomes full and a new line must be stored, the processor employs a replacement policy to decide which existing line to discard. The most common policy is Least Recently Used (LRU):

• LRU tracks the order of accesses and evicts the line that has not been used for the longest period.
• Other policies include First‑In‑First‑Out (FIFO), Random Replacement (RR), and Most‑Frequently‑Used (MFU), each with different performance trade‑offs.

LRU approximates the principle of temporal locality—recently accessed data is likely to be accessed again soon—making it a preferred choice for many modern CPUs.

Data Hazards in Superscalar Processors: The RAW Hazard

Superscalar architectures can issue multiple instructions per clock cycle, but they must respect data dependencies to avoid incorrect results. The RAW (Read After Write) hazard occurs when an instruction tries to read a register before a previous instruction has written the correct value to it.

Example:

1: ADD R1, R2, R3   ; R1 = R2 + R3
2: SUB R4, R1, R5   ; reads R1 before ADD completes → RAW hazard

To resolve RAW hazards, processors employ techniques such as operand forwarding, pipeline stalls, or out‑of‑order execution with register renaming.

Cache Locality Principles: Temporal and Spatial Locality

When a program accesses array elements sequentially, it benefits from two key cache locality concepts:

• Temporal locality: The same memory location is accessed repeatedly within a short time span.
• Spatial locality: Adjacent memory locations are accessed close together in time.

Sequential array traversal exhibits both forms: each element is accessed soon after the previous one (spatial), and the loop may revisit the same elements in later iterations (temporal). This dual locality explains the high cache hit rate observed in such patterns.

Control Bus (CBus) Functions in a Computer System

The Control Bus—sometimes referred to as the CBus—carries non‑data signals that coordinate the activities of the CPU, memory, and peripheral devices. Typical signals include:

• Read/Write commands that indicate the direction of a transfer.
• Clock and reset signals that synchronize operations.
• Interrupt acknowledge and bus arbitration signals that manage access contention.

Unlike the address or data buses, the CBus does not transport actual address values or payload data; instead, it ensures that every component knows when to listen, when to send, and how to interpret the information on the other buses.

Putting It All Together: How Memory, Buses, and Caches Interact

Modern computer architecture is a layered system where each component plays a specific role:

1. CPU Core issues instruction fetches and data reads/writes.
2. The address bus (ABus) conveys the target memory address to the memory controller (formerly the NorthBridge).
3. The control bus (CBus) signals whether the operation is a read or write and synchronizes timing.
4. The data bus (DBus) carries the actual instruction or data bytes once the memory subsystem responds.
5. On the way, the cache hierarchy (L1, L2, L3) may satisfy the request, using policies like LRU to keep the most useful lines.
6. If the request misses the cache, the memory controller accesses DRAM, which must be refreshed periodically to retain data integrity.

Understanding each of these steps helps students diagnose performance bottlenecks, design efficient algorithms, and appreciate why certain hardware choices—such as a wider address bus or a more sophisticated cache replacement policy—can dramatically affect overall system speed.

Key Takeaways for Students

• DRAM needs refresh because its bits are stored as charge in capacitors that leak over time; SRAM uses stable transistor latches.
• A 24‑line address bus can address up to 4 GiB of memory.
• The NorthBridge historically managed CPU‑memory communication and high‑speed I/O.
• Address information travels on the ABus, while the DBus carries data and the CBus carries control signals.
• Cache eviction commonly follows the Least Recently Used (LRU) policy.
• RAW hazards represent a Read‑After‑Write dependency that must be handled by the processor.
• Sequential array access benefits from both temporal and spatial locality.
• The CBus is responsible for control and synchronization, not for transporting addresses or data payloads.

Further Reading and Practice

To deepen your knowledge, explore the following resources:

• Wikipedia article on DRAM
• Wikipedia article on SRAM
• Intel Memory Architecture Overview
• Lecture notes on cache replacement policies
• Pipeline hazards and RAW dependencies

Try creating flashcards for each concept, and test yourself with the original quiz questions to reinforce learning.