MIPS Instruction Set Fundamentals

MIPS Instruction Set Fundamentals

Welcome to this comprehensive module on the MIPS (Microprocessor without Interlocked Pipeline Stages) instruction set. In this course we will explore the core design principles, instruction formats, register conventions, and typical coding patterns that make MIPS a classic example of a RISC architecture. By the end of the lesson you will be able to read simple MIPS assembly, understand why the ISA is built the way it is, and translate high‑level expressions into register‑level code.

Design Philosophy: Fixed‑Length Instructions and Three‑Operand Arithmetic

MIPS was created with a clear goal: simplicity and regularity. All instructions are exactly 32 bits long, and arithmetic operations always use three register operands (two sources and one destination). This uniformity brings several benefits:

• Simplified hardware encoding: The decoder sees a constant‑size word, so it can fetch, decode, and execute instructions in a predictable pipeline stage.
• Predictable timing: Each instruction typically completes in one clock cycle, which is essential for high‑frequency pipelines.
• Ease of compiler optimization: Compilers can generate code without worrying about variable‑length encodings or complex addressing modes.

Because of this design, the correct answer to the quiz question about the principle behind the single‑size, three‑operand rule is that it simplifies hardware encoding and improves regularity.

Instruction Formats: R‑type, I‑type, and J‑type

MIPS defines three primary instruction formats, each serving a distinct purpose:

• R‑type (Register): Used for register‑to‑register arithmetic and logical operations. It contains fields for opcode, rs, rt, rd, shamt, and funct.
• I‑type (Immediate): Holds a 16‑bit immediate value, making it ideal for constants, offsets, and simple memory accesses. The format includes opcode, rs, rt, and immediate.
• J‑type (Jump): Provides a 26‑bit address field for unconditional jumps.

The quiz correctly identifies the I‑type format as the one that uses an immediate field for constants or memory addresses.

Register Conventions in MIPS

MIPS provides 32 general‑purpose registers, each 32 bits wide. Understanding their conventional uses is crucial for writing clear assembly and for reading compiler‑generated code.

• $zero ($0): Hard‑wired to zero; reads as 0, writes are ignored.
• $at ($1): Reserved for assembler temporary.
• $v0‑$v1 ($2‑$3): Function return values.
• $a0‑$a3 ($4‑$7): Argument registers for function calls.
• $t0‑$t9 ($8‑$15, $24‑$25): Temporary values; caller‑saved.
• $s0‑$s7 ($16‑$23): Saved registers; callee‑saved.
• $k0‑$k1 ($26‑$27): Kernel reserved.
• $gp ($28): Global pointer.
• $sp ($29): Stack pointer.
• $fp ($30): Frame pointer.
• $ra ($31): Return address (not the program counter).

The false statement in the quiz is that "Register $31 is reserved for the program counter"—in reality, $31 holds the return address after a jal instruction.

Translating High‑Level Expressions to MIPS

Consider the C expression f = (g + h) - (i + j);. A typical compiler will allocate temporary registers for the two intermediate sums before performing the final subtraction. Following the conventional temporary register set, the compiler often uses $t0 and $t1:

    add $t0, $g, $h   # $t0 = g + h
    add $t1, $i, $j   # $t1 = i + j
    sub $f, $t0, $t1  # f = $t0 - $t1

Thus the correct answer to the quiz question about which registers hold the intermediate sums is $t0 and $t1.

Understanding a Simple MIPS Code Sequence

Examine the following three instructions:

    add $t0, $s1, $s2
    add $t0, $t0, $s3
    add $t0, $t0, $s4

Each add adds another source register to the accumulator stored in $t0. After the three statements, $t0 contains the sum of four values: $s1 + $s2 + $s3 + $s4. In high‑level terms this corresponds to the expression a = b + c + d + e. The quiz correctly identifies this as the implemented operation.

Why MIPS Uses a Small Register File

One might wonder why a RISC ISA would limit itself to only 32 general‑purpose registers. The answer lies in the trade‑off between hardware simplicity and pipeline speed:

• Fewer registers keep the register file small enough to be accessed in a single clock cycle, which is essential for a fast, pipelined datapath.
• A compact register file reduces the width of the instruction word needed to encode register numbers, helping maintain the fixed 32‑bit instruction size.
• Although a small register set may increase the need for memory accesses, the overall design goal is to keep the critical path short, thereby reducing the clock cycle time.

The quiz confirms this by selecting the statement that the primary advantage is a reduced clock cycle time.

Classifying MIPS: RISC vs. CISC

MIPS exemplifies the Reduced Instruction Set Computer (RISC) philosophy. Its hallmark traits include:

• Uniform instruction length (32 bits).
• Simple addressing modes (mostly register‑direct and base+offset).
• Load/store architecture: only lw and sw access memory.
• One‑cycle execution for most instructions.

Consequently, the correct classification in the quiz is RISC.

Operand Types in an "add" Instruction

The MIPS syntax add $s1, $s2, $s3 follows the destination‑source‑source order, and all three operands are registers. No immediate constants or memory addresses appear in this format. This matches the quiz answer that "All three operands are registers".

Key Takeaways

• Fixed‑size, three‑operand instructions simplify hardware and enable fast pipelines.
• MIPS uses three main formats: R‑type (register), I‑type (immediate), and J‑type (jump).
• Understanding register conventions ($t, $s, $a, etc.) is essential for reading and writing assembly.
• Translating C expressions to MIPS often involves using temporary registers for intermediate results.
• The small register file is a deliberate design choice to keep the clock cycle short.
• MIPS is a classic RISC architecture, distinguished from CISC and VLIW designs.

Further Study Recommendations

To deepen your mastery of MIPS, consider exploring the following topics:

• Pipeline hazards and how forwarding and stalls resolve them.
• Advanced addressing modes such as lui and ori for constructing 32‑bit constants.
• System calls and the role of the $v0 register in the MIPS syscall interface.
• Comparative analysis of MIPS with other RISC ISAs like ARM and RISC‑V.

Practicing by writing small programs, assembling them with spim or QtSPIM, and stepping through the execution will reinforce the concepts covered here.