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SSD Architecture and Performance

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1

Which type of flash memory cell stores the most bits per cell?

2

When a page is in the 'dirty' state, which operation can be performed on it?

3

What is the primary cause of write amplification in SSDs?

4

If an SSD has a page size of 4 KB and a block consists of 5 pages, how many kilobytes must be erased to free a single page?

5

During garbage collection, which of the following steps is the most costly?

6

Why does the performance of an SSD degrade as it fills up, even though its nominal speed is higher than an HDD?

7

Which SSD management technique spreads writes evenly across all blocks to prolong device life?

8

In a hybrid mapping scheme, how does the SSD handle a write to a logical block that was previously mapped at the block level?

9

What is the main purpose of the TRIM command in SSD operation?

10

A 1 TB SSD uses a 4‑byte entry per 4 KB page for mapping. Approximately how much DRAM is required for the mapping table?

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SSD Architecture and Performance

Review key concepts before taking the quiz

Understanding SSD Architecture and Performance

Solid‑State Drives (SSDs) have become the default storage solution for modern computers, laptops, and data‑center servers. Their speed, reliability, and low power consumption stem from a complex interplay of flash memory technology, controller algorithms, and firmware strategies. This course breaks down the most important concepts that affect SSD behavior, from the type of memory cells used to the sophisticated mapping schemes that keep the drive alive for years.

Flash Memory Cell Types

Flash memory stores bits in cells that can hold more than one bit per physical location. The number of bits per cell determines the trade‑off between density, cost, speed, and endurance.

  • Single‑Level Cell (SLC): 1 bit per cell – highest performance and endurance, but most expensive.
  • Multi‑Level Cell (MLC): 2 bits per cell – balances cost and performance.
  • Triple‑Level Cell (TLC): 3 bits per cell – common in consumer SSDs, lower endurance.
  • Quad‑Level Cell (QLC): 4 bits per cell – maximizes capacity and reduces price per gigabyte, but suffers the most from wear.

When choosing an SSD, consider the workload: high‑intensity write environments (e.g., databases) benefit from SLC or MLC, while archival storage can tolerate QLC.

Page States: The “Dirty” Page

SSD flash is organized into pages (typically 4 KB) that belong to larger blocks (often 256 KB‑2 MB). A page can be in one of three states:

  • Free: never programmed.
  • Valid: contains up‑to‑date data.
  • Dirty: data has been superseded by a newer write.

When a page becomes dirty, the only operation allowed is erasing the entire block that contains it. Individual pages cannot be erased; they must be rewritten as part of a block‑level erase cycle.

Write Amplification – The Core Performance Bottleneck

Write amplification (WA) occurs when the SSD writes more data to NAND than the host actually requested. The primary cause is the mismatch between the granularity of the file system (usually 4 KB sectors) and the granularity of NAND writes (entire pages and blocks).

Why does it happen?

  • The file system asks to modify a small 4 KB sector.
  • The SSD must read the whole block (e.g., 256 KB), merge the new data, and write the entire block back.
  • This read‑modify‑write cycle creates extra data traffic, inflating the amount of data written.

Mnemonic: “Granularità Grande = Amplificazione” – a large‑granularity SSD forced to handle small‑granularity writes leads to amplification.

Understanding WA is essential because it directly impacts endurance (more writes = faster wear) and throughput (extra internal I/O consumes bandwidth).

Erase Operations: How Much Must Be Erased?

Because NAND can only be erased at the block level, the size of a block determines the minimum amount of data that must be cleared before a new page can be written.

Example: If a page is 4 KB and a block contains 5 pages, the block size is 20 KB. To free a single page, the SSD must erase the whole 20 KB block, even though only 4 KB of that data is actually needed.

This block‑erase requirement is a key driver of write amplification and influences the design of wear‑leveling algorithms.

Garbage Collection – The Most Costly Step

Garbage collection (GC) reclaims space occupied by dirty pages. The process involves three main steps:

  1. Identify blocks with a mix of valid and invalid pages.
  2. Read the live (valid) data from those partially dirty blocks.
  3. Write the live data to a new clean block and erase the old block.

The reading of live data is the most expensive operation because it adds extra I/O, consumes controller bandwidth, and may trigger additional write amplification.

Mnemonic: “Leggi i vivi, paga il prezzo” – reading the valid pages is the price you pay during GC.

Why SSD Performance Degrades as the Drive Fills Up

Even though SSDs have higher nominal speeds than HDDs, their performance drops when the free‑space pool shrinks. The root cause is an increase in write amplification:

  • Fewer empty pages mean the controller must relocate more existing data to make room for new writes.
  • Each relocation adds extra reads and writes, consuming bandwidth and increasing latency.

Mnemonic: “PAGINE Piene → Più Amplificazione → Prestazioni Piane”.

Best practice: keep at least 10‑20 % of the SSD capacity free to maintain low WA and high throughput.

Wear Leveling – Extending SSD Lifetime

Every NAND block can endure only a limited number of program/erase (P/E) cycles. Wear leveling spreads writes evenly across all blocks, preventing hot spots that would wear out early.

How it works

  • The controller tracks erase counts for each block.
  • When a block reaches a higher erase count, new writes are redirected to less‑used blocks.
  • Data may be moved (via GC) to balance wear without affecting the host.

Mnemonic: Wear Leveling → Write Like Water, spread the writes across the whole garden.

Hybrid Mapping Schemes – Combining Block and Page Mapping

Pure block mapping is fast for reads but inefficient for writes, while pure page mapping offers fine‑grained write flexibility at the cost of larger mapping tables. Hybrid schemes blend the two:

  • Read operations use block‑level mapping for speed.
  • Write operations use page‑level mapping, creating a new log block for each update.
  • The mapping table is updated only for the pages that changed, keeping the overhead low.

When a logical block that was previously mapped at the block level receives a new write, the SSD does not erase the whole block. Instead, it allocates a fresh log block, writes the new page, and updates the page‑mapped table to point to the new location.

Mnemonic: “Log‑Block, Pag‑Update” – think of adding a new page in a log rather than scrubbing the whole block.

Key Takeaways

  • Cell density matters: SLC > MLC > TLC > QLC in performance and endurance.
  • Dirty pages can only be cleared by erasing their entire block.
  • Write amplification is driven by the mismatch between file‑system sector size and NAND block size.
  • Erasing a block removes all its pages; the smallest erasable unit is the block, not the page.
  • During garbage collection, reading live data is the most I/O‑intensive step.
  • As an SSD fills, write amplification rises, causing slower writes and higher latency.
  • Wear leveling distributes P/E cycles to extend device life.
  • Hybrid mapping leverages fast block reads and flexible page writes, using log blocks to avoid costly full‑block erases.

By mastering these concepts, you can make informed decisions about SSD selection, configuration, and maintenance, ensuring optimal performance and longevity for any computing environment.

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