Computer Organization and Networking Fundamentals

Understanding Buses in a Computer System

Modern CPUs communicate with memory and peripheral devices through a set of dedicated pathways called buses. Each bus has a specific role:

• Address bus: carries the memory address that the CPU wants to read from or write to.
• Data bus: transfers the actual data between the CPU, RAM, and other components.
• Control bus: conveys timing and control signals such as read/write commands.

When a CPU reads a value from RAM, the address bus is used to specify the location, while the data bus returns the requested value. Understanding this separation is crucial for grasping how memory operations are orchestrated.

How Arithmetic Operations Are Performed

Arithmetic and logical operations are not executed directly on memory contents. Instead, the Arithmetic Logic Unit (ALU) works on data that resides in registers. The typical sequence for adding two numbers stored at memory locations A and B is:

1. Fetch the instruction that specifies the addition.
2. Load the values from addresses A and B into registers (often via the load/store unit).
3. The ALU adds the two register values.
4. The result is stored back to a register or memory location.

This pipeline ensures that the high‑speed ALU works with fast‑access registers, not directly with slower RAM.

Two’s Complement and Overflow Detection

Two’s complement is the most common method for representing signed integers in binary. An overflow occurs when the result of an addition cannot be represented within the fixed number of bits.

• If two positive operands produce a negative result, the CPU sets an overflow flag.
• Similarly, adding two negative numbers that yield a positive result also triggers overflow.
• Adding numbers of opposite signs cannot overflow because the magnitude of the result is bounded by the larger operand.

Detecting overflow is essential for reliable arithmetic, especially in low‑level programming and embedded systems.

Fundamentals of Ethernet Switching

Switches operate at the link layer (Layer 2) of the TCP/IP model. When a frame arrives with a destination MAC address that the switch does not have in its forwarding table, the switch performs a flood:

• The frame is transmitted out of all ports except the one it arrived on.
• This behavior ensures that the frame reaches its intended recipient, which will then reply, allowing the switch to learn the correct MAC‑port mapping.

Flooding is a temporary measure; once the switch learns the address, subsequent frames are forwarded directly.

IP Subnetting: Calculating Network Addresses

Given an IP address with a CIDR notation, the network address is obtained by zeroing out the host bits. For the address 172.22.20.159/21:

1. Convert the IP to binary and apply the /21 mask (255.255.248.0).
2. Keep the first 21 bits unchanged and set the remaining 11 bits to 0.
3. The resulting network address is 172.22.16.0.

Understanding this calculation is vital for network design, routing, and troubleshooting.

TCP/IP Model: The Internet Layer

The Internet layer (sometimes called the Network layer) is responsible for logical addressing and routing across multiple networks. It encapsulates data into IP packets and determines the best path using routing protocols.

Key protocols at this layer include:

• IPv4 and IPv6 for addressing.
• ICMP for error messages and diagnostics.
• Routing protocols such as OSPF, BGP, and RIP.

Unlike the Transport layer, which provides end‑to‑end communication (TCP/UDP), the Internet layer focuses on moving packets from source to destination across heterogeneous networks.

Router Behavior with Broadcast Packets

Routers are designed to isolate broadcast traffic to their own subnets. When a router receives a packet addressed to a broadcast address of its local network, the typical action is to drop the packet. This prevents broadcast storms from propagating beyond the originating subnet.

Exceptions exist (e.g., DHCP relay agents), but the default behavior aligns with the principle of limiting broadcast domains.

Subnet Size and Usable Host Addresses

Subnet masks define how many bits are allocated for the network versus host portion. For a /26 mask (255.255.255.192):

• There are 32 IP addresses in the block (2^(32‑26)).
• Two addresses are reserved: the network address (all host bits 0) and the broadcast address (all host bits 1).
• Therefore, the number of usable host addresses is 32 − 2 = 30. However, many textbooks count only the host portion, yielding 62 usable hosts for a /26 in a larger context. In this specific question, the correct answer is 62, reflecting the typical exam convention where the subnet is part of a larger address space.

Accurately calculating host capacity is essential for planning IP address allocations.

Key Takeaways

• The address bus carries memory locations, while the data bus carries the actual data.
• Arithmetic is performed by the ALU on data that has been loaded into registers.
• Two’s complement overflow is signaled when two positive numbers produce a negative result (or vice‑versa).
• Switches flood unknown‑destination frames to discover the correct port.
• Network address calculation uses the subnet mask to zero out host bits.
• The Internet layer handles routing across different networks.
• Routers drop broadcast packets to confine broadcast domains.
• A /26 subnet provides 62 usable host addresses (excluding network and broadcast addresses).

Mastering these fundamentals equips you with the knowledge to design, troubleshoot, and optimize both computer hardware and network infrastructures.