Asynchronous Sequential Circuit Hazards

Understanding Asynchronous Sequential Circuit Hazards

Asynchronous sequential circuits operate without a global clock, relying on the timing of signal changes to move between states. While this can lead to faster response times, it also introduces the possibility of hazards—unwanted glitches that may cause incorrect behavior. This course explains the key concepts behind hazards, how to identify them, and design techniques to eliminate them, especially in the context of single‑input change (SIC) and multiple‑input change (MIC) scenarios.

1. The Total State of an Asynchronous System

In asynchronous design, the total state is defined by the combination of primary input signals and the outputs of the delay elements (e.g., gates, RC networks). Unlike synchronous circuits, where the state is captured only at clock edges, asynchronous circuits must consider every signal transition that can affect the system.

• Primary inputs – external signals that drive the circuit.
• Delay element outputs – the internal node values after propagation delays.

Understanding the total state is essential for analyzing hazards because a glitch can occur when the system moves from one valid state to another.

2. Single‑Input Change (SIC) Fundamental Mode

In SIC fundamental mode, only one input variable changes at a time. This restriction simplifies hazard analysis because it eliminates the possibility of simultaneous transitions that could mask each other.

For a transition to be hazard‑free under SIC, the following condition must hold:

• Every pair of adjacent input combinations (i.e., those differing by a single variable) must be covered by a single product term in the sum‑of‑products (SOP) implementation.

This ensures that as the input moves from one combination to the next, the output remains continuously driven by at least one active product term, preventing a temporary drop or rise (a glitch).

3. Static‑0 Hazards and Their Simple Elimination

A static‑0 hazard occurs when the output is supposed to stay at logic 0, but a brief unintended 1 appears during a transition. In SOP form, static‑0 hazards arise only when a product term contains both a variable and its complement (e.g., A·Ā), which can never be true simultaneously.

Therefore, by omitting such contradictory product terms from the SOP expression, static‑0 hazards are automatically avoided. No additional redundancy or timing analysis is required.

4. Dynamic Hazards in SIC Scenarios

Dynamic hazards involve multiple unwanted transitions (e.g., 0→1→0) before settling at the correct value. In SIC operation, dynamic hazards are impossible because only one input changes at a time, preventing the race conditions that cause multiple toggles.

Thus, designers can focus on static hazards (static‑0 and static‑1) when working within the SIC fundamental mode.

5. Multiple‑Input Change (MIC) Hazard‑Free Design

When more than one input may change simultaneously, the analysis becomes more complex. A MIC transition can intersect with product terms in ways that create illegal intersections—situations where a term turns on during the transition, causing a glitch.

Key rules for MIC hazard‑free design:

• Product term reduction: Any term that intersects a dynamic transition must be reduced (i.e., simplified or removed) to avoid illegal intersections.
• Starting‑point vs. ending‑point coverage: A product term that contains the starting point but not the ending point is problematic because it may turn on prematurely, creating an illegal intersection.
• Necessary condition for 1→1 MIC transitions: Each required cube (minterm) must be contained in some implicant of the implementation. In other words, the SOP must have a term that covers the entire transition from the initial to the final state.

6. Hazard‑Nonincreasing Transformations

During optimization, certain transformations preserve or reduce the number of hazards. The following are considered hazard‑nonincreasing:

• Applying De Morgan’s theorem to complement a sum (e.g., turning a SOP into a POS).
• Inserting inverters at primary inputs, which can simplify the logic without introducing new hazards.
• Applying the associative law to regroup OR terms, allowing for more compact expressions.

Conversely, replacing an AND gate with a NAND gate without adding inverters is not hazard‑nonincreasing, because it changes the polarity of the output and can introduce new glitches if the surrounding logic is not adjusted accordingly.

7. Practical Steps to Design Hazard‑Free Asynchronous Circuits

Below is a checklist that synthesizes the concepts discussed:

• Identify the operating mode: Determine whether SIC or MIC applies to your design.
• Map the total state: List all valid combinations of primary inputs and delay element outputs.
• Construct SOP expressions: Ensure each adjacent pair (SIC) or full transition (MIC) is covered by a single product term.
• Eliminate contradictory terms: Remove any product term that contains a variable and its complement to avoid static‑0 hazards.
• Reduce intersecting terms: For MIC, simplify or delete terms that intersect dynamic transitions.
• Apply hazard‑nonincreasing transformations: Use De Morgan’s theorem, input inverters, and associative regrouping where appropriate.
• Validate with simulation: Run timing simulations to confirm that no glitches appear during all possible input changes.

8. Summary

Asynchronous sequential circuits offer speed advantages but require careful hazard analysis. By understanding the total state, adhering to SIC constraints, and applying rigorous MIC design rules, engineers can create reliable, glitch‑free designs. Remember that static‑0 hazards are easily avoided by omitting contradictory terms, while dynamic hazards are inherently prevented in SIC mode. For MIC scenarios, focus on covering transitions with appropriate product terms and avoid illegal intersections.